1. Field of the Invention
The present invention relates to semiconductor devices, in particular, to non-volatile memory devices.
2. Description of the Related Art
In Application Specific Integrated Circuits (ASICs), it is often desirable to incorporate a low-cost, low-density, non-volatile memory device or memory array. However, process complexity hinders the incorporation of traditional non-volatile memory devices and memory arrays (e.g., traditional electrically-programmable read-only memory [EPROM] devices) into Metal-Oxide-Semiconductor (MOS) ASICs. The need for multiple polysilicon layers, various gate silicon dioxide (SiO2) thicknesses, and/or non-standard junction doping profiles in traditional non-volatile memory devices, for example, increases process complexity and cost.
To overcome these drawbacks, a non-volatile memory device 10 that utilizes standard CMOS transistors has been proposed, as illustrated in FIG. 1. This conventional non-volatile memory device 10 includes a PMOS transistor 12 configured in series with an NMOS access transistor 14.
In PMOS transistor 12, no electrical contact is made to the polysilicon gate 16, which therefore acts as a xe2x80x9cpolysilicon floating gatexe2x80x9d. Because the polysilicon gate 16 of the PMOS transistor is a polysilicon floating gate, PMOS transistor 12 can function as a storage device and is alternatively referred to as a xe2x80x9cPMOS storage transistorxe2x80x9d 12. The source 18 of the PMOS storage transistor 12 is configured to be electrically connected to VSS (a negative power supply terminal), or ground (GND), and to VCC (a power supply terminal, also commonly referred to as VDD) during programming and reading of the conventional non-volatile memory device 10.
NMOS access transistor 14 has a polysilicon gate 20 that is also configured to be electrically connected to both VSS and VCC during programming and reading of the conventional non-volatile memory device 10. NMOS access transistor 14 also includes a drain 22 that is electrically connected to VSS (a negative power supply terminal) or ground (GND). The NMOS access transistor 14 is, therefore, configured to provide for the selective programming of the PMOS storage transistor 12. A further discussion of conventional non-volatile memory device 10 and its operation is available in Albert Bergemont et al., A Non-Volatile Memory Device with True CMOS Compatibility, Electronics Letter, Vol. 35, no. 17. 1443-5 (IEE, Aug. 19, 1999), which is hereby fully incorporated by reference.
FIG. 2 is a plan view of a layout for a conventional non-volatile memory device 40 that is essentially equivalent to the electrical schematic of FIG. 1. As shown in FIG. 2, this conventional non-volatile memory device 40 includes a PMOS transistor 42 (i.e., a PMOS xe2x80x9cstoragexe2x80x9d transistor 42) that includes a P-type source region 44 and a P-type drain region 46, which are spaced apart from each other. The P-type source region 44 and the P-type drain region are formed in an N-type well region 48, and a channel region 50 is defined between the P-type source region 44 and the P-type drain region 46. PMOS storage transistor 42 also includes a polysilicon floating gate 52.
Conventional non-volatile memory device 40 also includes an NMOS access transistor 54 with a N-type source region 56 and a N-type drain region 58, which are spaced apart from each other. The N-type source region 56 and N-type drain region 58 are formed in a P-type semiconductor material (e.g., a P-type well region or P-type wafer substrate), and a channel region 62 is defined between the N-type source region 56 and the N-type drain region 58. NMOS access transistor 54 also includes a polysilicon gate 64.
In the conventional non-volatile memory device 40 of FIG. 2, the N-type source region 56 of the NMOS access transistor 54 is electrically connected to the P-type drain region 46 of the PMOS storage transistor 42 via a metal interconnect line 66 (commonly referred to as a metal xe2x80x9cstrapxe2x80x9d). Furthermore, a contact 67 is provided to electrically connect the N-type drain region 58 to GND/VSS, a contact 68 is provided to electrically connect the polysilicon gate 64 to VCC/VSS, a contact 70 is provided to electrically connect the P-type source region 44 to VCC/VSS and a contact 71 is provided to electrically connect the N-type well region 48 to VCC/VSS.
Conventional non-volatile memory device 40 can also be represented in a combined cross-sectional and schematic manner as depicted in FIG. 3, wherein like reference numerals from FIG. 2 are used to refer to like elements. In FIG. 3, the conventional non-volatile memory device 40 is formed in a P-type semiconductor material (e.g., a P-type well region or a P-type wafer substrate) 72. The conventional non-volatile memory device 40 includes an N-type well region 48 disposed in the P-type semiconductor material 72 and electrically connected to VCC/VSS via N-type contact region 74.
The PMOS storage transistor 42 includes spaced-apart P-type source and drain regions 44 and 46, respectively, a channel region 50 disposed therebetween, and a polysilicon floating gate 52. The NMOS access transistor 54 includes an N-type source region 56, an N-type drain region 58, a channel region 62 disposed therebetween and a polysilicon gate 64.
Both the N-type drain region 58 and the P-type semiconductor material 72 are electrically connected to GND/Vss. The P-type semiconductor material 72 is connected to GND/Vss via a P-type contact region 76. The N-type source region 56 of the NMOS access transistor 54 is electrically connected to the P-type drain region 46 of the PMOS storage transistor 42 via a metal interconnect line 66 (a metal xe2x80x9cstrapxe2x80x9d). Electrical isolation region 78 (e.g., a field oxide isolation region or a trench isolation region) provides isolation between PMOS storage transistor 42 and the NMOS access transistor 54.
Frequently, the conventional non-volatile memory devices 10 (see FIG. 1) are configured in a conventional non-volatile memory array 80, as illustrated in FIG. 4. Non-volatile memory array 80 includes a plurality of traversing bit lines 82 and word lines 84, each of which can be electrically connected to VCC/VSS. In non-volatile memory array 80, each of the non-volatile memory devices 10 is electrically connected to a bit line 82 and a word line 84. The polysilicon gates 20 of the NMOS access transistors 14 are each electrically connected to a word line 84. The source 18 of the PMOS storage transistors 12 are each electrically connected to a bit line 82. When a word line 84 is at VSS, the electrically connected NMOS access transistors 14 are in an OFF state and no programming of the PMOS storage transistor can take place. However, when a word line 84 is at VCC, the electrically connected NMOS access transistors 14 are in an ON state and programming of the PMOS storage transistor can take place depending on the state (VCC or VSS) of the bit line.
For a further discussion of known non-volatile memory devices and known non-volatile memory arrays, see U.S. Pat. No. 6,055,185 to Kalnitsky et al. and Bergemont et al. supra, both of which are hereby incorporated by reference as if fully set forth.
A drawback of conventional non-volatile memory device 10 is its relatively large size. This relatively large size is due primarily to the need to connect the P-type drain of the PMOS storage transistor to the N-type source of the NMOS access transistor via a metal interconnect line. The relatively large size is also due, however, to a required spacing between the N-type source region of the NMOS access transistor and the N-type well region, in which the PMOS storage transistor is formed.
Still needed in the field, therefore, is a compact non-volatile memory device and memory array. In addition, the compact non-volatile memory device should be compatible with conventional MOS device processing.
The present invention provides a compact non-volatile memory device and a compact non-volatile memory array that can be fabricated using processes that are fully compatible with conventional MOS device processing. Therefore, compact non-volatile memory devices and compact non-volatile memory arrays according to the present invention can be easily embedded in MOS logic circuits, MOS mixed-signal circuits and MOS ASIC circuits.
Compact non-volatile memory devices according to the present invention include a PMOS storage transistor with a floating gate and a PMOS access transistor with a gate. Furthermore, the PMOS storage transistor and PMOS access transistor are electrically connected in series. Since both the PMOS storage transistor and the PMOS access transistor can be disposed in a single N-type well region, the size of the compact non-volatile memory devices is relatively small in comparison to conventional non-volatile memory devices.
Also provided by the present invention is a compact non-volatile memory device formed in a semiconductor substrate (e.g., a semiconductor wafer or a well region) of a first conductivity type (typically P-type). The compact non-volatile memory device includes a well region of a second conductivity type (typically N-type) disposed in the semiconductor substrate. Also included in the compact non-volatile memory device are a first source region of the first conductivity type, a first drain region of the first conductivity type, a first channel region defined therebetween, and a floating gate formed over the first channel region. Each of the first source region, first drain region and first channel region is formed in the well region.
The compact nonvolatile memory device also includes a second source region of the first conductivity type, a second drain region of the first conductivity type, a second channel region defined therebetween, and a gate formed over the second channel region. Each of the second source region, second drain region and second channel region is formed in the well region.
Since the first and second source regions, first and second drain regions, and first and second channel regions are all formed in a single well region, compact non-volatile memory devices according to the present invention are of a relatively small size.
A compact non-volatile memory array according to the present invention is also provided and includes a plurality of traversing (e.g., crisscrossing) bit lines and word lines and a plurality of compact non-volatile memory devices.
Each of the compact non-volatile memory devices includes a PMOS storage transistor with a floating gate and a source and a PMOS access transistor with a gate. The PMOS access transistor is connected in series with the PMOS storage transistor. In addition, each of the compact non-volatile memory devices is electrically connected to one of the bit lines via the source of the PMOS access transistor and electrically connected to one of the word lines via the gate of the PMOS access transistor.